招聘职位
Staff DV Engineer
- 公 司：NO.352-A development solution design and manufacturing company
- 工作地点：上海
- 发布日期：2019-04-04
- 职位编号：4038
- 有效状态：已关闭
职位描述
Job Tasks
Work with designer to get a full deep insight on the design and develop stressful test plan for SoC and IPs
Build test bench and create testcase to ensure maximum coverage
Run simulation in both RTL and netlist level, debug and fix issues, create test reports.
Develop verification IP which can be reused at different level verification
Co-work with FPGA engineer to prepare test vector, support test and debug
SoC system performance profiling, system stress test
Explore advanced verification methodology, optimize the verification process/environment to improve efficiency and quality
Support DV manager to do the verification quality control and sign-off the DV task
职位要求
Qualifications
Must Have
MSEE/MSCS degree or equivalent
Minimum 8 years’ experience in design verification field
· Good knowledge in SystemVerilog, C/C++ and UVM
· Good knowledge in the SoC architecture, AXI/AHB protocol. Experienced in full chip verification plan, execution and sign-off.
· Experienced in system performance test
· Strong communications skills and capability
Self-motivated and good team player
Nice to have
· Strong Programming in Perl, Python
· Good digital signal processing background and be familiar with video processing algorithm, be familiar with MATLAB
· Experienced in low power verification
· Be familiar with FPGA debug.