招聘职位
芯片设计
- 公 司：NO.341-The world’s first consumer-grade 16nm ASIC miner
- 工作地点：上海
- 发布日期：2018-05-10
- 职位编号：4040
- 有效状态：已关闭
职位描述
1. Participate in RISCV or Deep Learning Accelerator or other SOC IP design for all frontend phase
2. Specification define
3. RTL implementation
4. Analysis and optimization for performance
5. Analysis and optimization for power
6. Analysis and optimization for timing
7. Design flow: lint/synthesis/sta/formal check
8. Silicon debugging
职位要求
1. MS with 5+ or 3+ years of experience in ASIC design
2. Experience with RISC CPU (RISCV/MIPS/ARM) related IPs design are highly desirable
3. Experience with USB/MIPI_CSI/MIPI_DSI or other high speed interface IPs design are highly desirable
4. Experience with Deep Learning Accelerator related IPs design are highly desirable
5. Experience with all phases of frontend architecture, design and validation
6. RTL Coding, design reviews, SYN, CDC, FEV
7. Demonstrated work experience with timing analysis, area and power optimizations, performance analysis, debug ability, ECOs, and post-silicon debug
8. Excellent knowledge of Verilog and popular EDA simulation & implementation tools
9. Good experience in scripting languages like Perl, Unix shell or similar languages