招聘职位
Principal serdes design engineer
- 公 司：NO.73-One world top EDA company
- 工作地点：南京
- 发布日期：2018-11-15
- 职位编号：4058
- 有效状态：已关闭
职位描述
- Design, simulation and verification of high speed serdes at data rates of 10Gb/s and higher.
- High speed blocks AMS modeling and support IP verification in digital top
- Define specifications of IC blocks and create design documentation.
- Design of IC blocks and supervise layout floor plan.
- Silicon test, characterization and lab debugging.
- Knowledge sharing within design team
职位要求
MSEE or above with minimum 5+ years of working/research experience in high-speed CMOS SerDes design (CTLEs, PLLs, DFEs, etc.)；
Experience in high speed designs (e.g. USB3.0/3.1, PCIe, HDMI, SATA, DisplayPort, SerDes) preferred.
Strong lab experience on silicon debugging, good understanding on lab instruments (e.g oscilloscope, Error Bert)
Good understanding of high-speed layout considerations, such as parasitic, crosstalk isolation, supply and bias distribution, etc.
Proficient with Cadence design environment and mixed-signal simulation (ADE, Layout, AMS), mixed-signal simulation (AMS), EM simulation (such as EMX)
Working knowledge of theoretical and practical aspects of electro-magnetic structures including transmission lines, spiral inductors, resonant circuits, etc. (HFSS experience is a plus)
Able to assume responsibility for a variety of technical tasks and to work independently
Able to be hands-on at all levels of design, with the ability to verify, test, and characterize own designs
Good communication skill and good command of written English are highly desired.