招聘职位
Senior ASIC engineer
- 公 司:NO.270-a start up company with innovative technology
- 工作地点:上海
- 发布日期:2013-04-19
- 职位编号:3171
- 有效状态:已关闭
职位描述
职位要求
5 + years experience in ASIC design -> must
· MS in Electrical Engineering (or equivalent) is a must have
· Experience with WIFI baseband/MAC or related wireless baseband technology desired -> plus
· System on Chip (SOC) Integration Experience, including AHB/AXI, CPU integration -> plus
· Experience with interfaces such as SPI, SDIO, USB -> plus
· Working knowledge of networking protocols such as TCP/IP, 802.3, 802.11 -> plus
· Must be expert in Verilog RTL language -> must
· Must be familiar with the ASIC design flow from RTL through synthesis, including the tool flow. -> must
· Verification experience – Verilog, System-Verilog, Coverage Analysis -> must for verification engineer, plus for design engineer
· FPGA emulation experience -> plus
· Chip bring-up experience, including use of Logic Analyzer and Oscilloscope for debugging -> plus
· Experience with digital backend