招聘职位
Digital Design Engineers for Mixed-Signal Power Management ASICs
- 公 司：NO.54-A famous IC company
- 工作地点：新加坡
- 发布日期：2013-06-06
- 职位编号：3199
- 有效状态：已关闭
职位描述
Responsibilities
Successful candidates will be responsible for leading, and participating in, the design and verification of leading edge ASICs in advanced digital CMOS processes for multi-function mobile platforms.
职位要求
Skills/Experience
Design candidates will have a minimum of 2-3 years of relevant experience and must have detailed knowledge of digital ASIC design including architecture, RTL design for control and signal processing functions, linting, synthesis, STA, and DFT. Design candidates must also have experience with leading-edge ASIC development tools from Synopsys, Mentor, or Cadence. Experience designing mixed signal interfaces and integrating digital modules into mixed-signal ASICs is desirable. Verification candidates should have a minimum of 2-3 years of relevant experience and must have detailed knowledge of self-checking testbench architectures (including directed and random-constrained generation) and coverage-driven verification techniques at the functional, assertion and code levels. Verification candidates will also have a working understanding of Object Oriented System Verilog principles. Experience with VMM, OVM, or UVM is desirable as is experience verifying digital modules in mixed-signal ASICs.
Education Requirements
Bachelor''s degree in Electrical Engineering required. Master''s degree in Electrical Engineering preferred.