Job Request
1. MS with 5+ or 3+ years of experience in ASIC design
2. Experience with RISC CPU (RISCV/MIPS/ARM) related IPs design are highly desirable
3. Experience with USB/MIPI_CSI/MIPI_DSI or other high speed interface IPs design are highly desirable
4. Experience with Deep Learning Accelerator related IPs design are highly desirable
5. Experience with all phases of frontend architecture, design and validation
6. RTL Coding, design reviews, SYN, CDC, FEV
7. Demonstrated work experience with timing analysis, area and power optimizations, performance analysis, debug ability, ECOs, and post-silicon debug
8. Excellent knowledge of Verilog and popular EDA simulation & implementation tools
9. Good experience in scripting languages like Perl, Unix shell or similar languages