招聘职位
Verification engineer[系统编号：620142821953]
- 公 司：NO.196-A famous European IC company
- 工作地点：上海
- 发布日期：2012-11-02
- 职位编号：2803
- 有效状态：已关闭
职位描述
Roles and Responsibilities <br>
Verification of digital and mixed-signal circuits (module-level and chip-level)<br>
Definition of verification plans and verification environments for mixed-signal sensor systems<br>
Tracking and management of verification progress and coverage<br>
Close cooperation and interaction with international teams<br>
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职位要求
Qualification Requirement <br>
(e.g. Education, Working Experience, Knowledge, Skills, Language, Competence, etc)<br>
Bachelor or master degree in (Micro-)Electronics, Communications, Computer Engineering or equivalent, 3+ years <br>
Experience of large scale IP/SoC verification, or experience in development of automated test-bench<br>
Hands-on experience of C/C++ programming language is preferred<br>
Self motivated, excellent communication skills and a real team player<br>
English written and verbal<br>
Understand of / experience with at least one of following domains:<br>
Makefile/Perl/Python scripting<br>
SystemVerilog or SystemC or Specman-e verification language, experience in UVM is preferred<br>
VerilogAMS, Cadence AMSD, Mixed-signal simulation