招聘职位
Principle Design Engineer（Shanghai）
- 公 司：NO.73-One world top EDA company
- 工作地点：上海
- 发布日期：2012-08-29
- 职位编号：2912
- 有效状态：已关闭
职位描述
- Be responsible for the design micro-architecture, system and test platform development
- Proficiency in logic design, simulation
- Proficiency in Verilog and its simulation environment
At least six years experience on driving complex IC development projects on wired/wireless telecom and high speed interface, excellent communication skills and the uncanny ability to both lead and contribute in a cooperative team environment is required.
职位要求
Have BS degree with 12+ years of applicable experience, MS degree with 10+ years of applicable experience or PhD degree with 6+ years of applicable experience in architecture and system.
Strong knowledge with DSP and mixed signal design in Digital communication, DTV or Multimedia.
Must have strong Mathematics skill. Knowledge of Matlab, or C/C++, or System C, SystemVerilog or Verilog is necessary.
Experience of DSP based Architecture design. Good Knowledge of CPU, DSP and GPU.
Good knowledge on wired high-speed interface standard
Ability to work effectively alone or as well as in a team.
Essential that the individual demonstrates strong communication, verbal and written