Job
验证工程师
- Company：No.615
- Location：北京
- Date of post：2023-12-19
- Job No：4153
- Valid Status：Opening
Job Description
1.Understand the expected functionality of designs;
2.Design and develop verification environment;
3.Run RTL and gate-level simulations/regression;
4.Code/functional coverage development, analysis and closure;
5.Release the documents during the verification flow, such as verification plan, usage of the verification environment, simulation result of test cases, verification coverage report, etc.
Job Request
1.Minimum of 4 years design/verification experience (test plan, test bench, assertions, debugging designs, code coverage etc.);
2.Familiar with design and verification languages (Verilog, System Verilog, UVM etc.);
3.Script and automation skills (tcl, perl, makefile etc) a plus;
4.Additional qualifications include: Good IC verification skills and basic knowledge of logic or circuit design;
5.Independent and self-management;
6.Cooperative and proactive in daily work.